View DS1374C-33_100992.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Rev 1; 9/04
I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output
General Description
The DS1374 is a 32-bit binary counter designed to continuously count time in seconds. An additional counter generates a periodic alarm or serves as a watchdog timer. If disabled, this counter can be used as 3 bytes of nonvolatile (NV) RAM. Separate output pins are provided for an interrupt and a square wave at one of four selectable frequencies. A precision temperature-compensated reference and comparator circuit monitor the status of VCC to detect power failures, provide a reset output, and automatically switch to the backup supply when necessary. Additionally, the reset pin is monitored as a pushbutton input for externally generating a reset. The device is programmed serially through an I2CTM serial interface.
Features
32-Bit Binary Counter Second Binary Counter Provides Time-of-Day Alarm, Watchdog Timer, or NV RAM Separate Square-Wave and Interrupt Output Pins I2C Serial Interface Automatic Power-Fail Detect and Switch Circuitry Single-Pin Pushbutton Reset Input/Open-Drain Reset Output Low-Voltage Operation Trickle-Charge Capability -40C to +85C Operating Temperature Range 10-Pin SOP, 16-Pin SO Available in a Surface-Mount Package with an Integrated Crystal (DS1374C) Underwriters Laboratory (UL) Recognized
DS1374
Applications
Portable Instruments Point-of-Sale Equipment Medical Equipment Telecommunications
Typical Operating Circuit
PART
VCC RPU = tr/CB VCC CRYSTAL
Ordering Information
TEMP RANGE PINPACKAGE TOP MARK DS1374-18 DS1374-3 DS1374-33
DS1374U-18 DS1374U-3 DS1374U-33
X1 SCL X2 VCC SQW
-40C to +85C 10 SOP -40C to +85C 10 SOP -40C to +85C 10 SOP
RPU RPU VCC
DS1374C-18 DS1374C-3 DS1374C-33
-40C to +85C 16 SO, 0.300" DS1374C-18 -40C to +85C 16 SO, 0.300" DS1374C-3 -40C to +85C 16 SO, 0.300" DS1374C-33
CPU INT
SDA INT
DS1374
PRIMARY BATTERY, RECHARGEABLE BATTERY, OR SUPER CAPACITOR
RST N.O. PUSHBUTTON RESET
RST
VBACKUP GND
Pin Configurations appear at the end of the data sheet.
I 2 C is a trademark of Philips Corp. Purchase of I 2 C components of Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I 2 C system, provided that the system conforms to the I 2 C Standard Specification as defined by Philips. ______________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output DS1374
ABSOLUTE MAXIMUM RATINGS
Voltage Range on VCC Pin Relative to Ground .....-0.3V to +6.0V Voltage Range on SDA, SCL, and WDS Relative to Ground ....................................-0.3V to VCC + 0.3V Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-55C to +125C Soldering Temperature Range ........................See the Handling, PC Board Layout, and Assembly section.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(VCC = VCC MIN to VCC MAX, TA = -40C to +85C, unless otherwise noted.) (Note 1)
PARAMETER Supply Voltage (Notes 2, 3) Input Logic 1 Input Logic 0 Pullup Resistor Voltage (INT, SQW, SDA, SCL), VCC = 0V Power-Fail Voltage (Note 2) SYMBOL DS1374-33 VCC VIH VIL VPU DS1374-3 DS1374-18 (Note 2) (Note 2) (Note 2) DS1374-33 VPF DS1374-3 DS1374-18 DS1374-33 Backup Supply Voltage (Notes 2, 3, 4) VBACKUP DS1374-3 2.70 2.45 1.51 1.3 1.3 2.88 2.6 1.6 3.0 3.0 CONDITIONS MIN 2.97 2.7 1.71 0.7 x VCC -0.3 TYP 3.3 3.0 1.8 MAX 5.50 3.3 1.89 VCC + 0.3 +0.3 x VCC 5.5 2.97 2.7 1.71 VCC
MAX
UNITS V V V V
V
3.7
V
2
_____________________________________________________________________
I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output
DC ELECTRICAL CHARACTERISTICS
(VCC = VCC MIN to VCC MAX, TA = -40C to +85C, unless otherwise noted.) (Note 1)
PARAMETER Trickle-Charge Current-Limiting Resistors Input Leakage I/O Leakage RST Pin I/O Leakage SDA Logic 0 Output (VOL = 0.4V) RST, SQW, and INT Logic 0 Outputs (Note 11) SYMBOL R1 R2 R3 ILI ILO ILORST IOLSDA VCC > 2V; VOL = 0.4V IOL1 1.71V < VCC < 2V; VOL = 0.2 VCC 1.3V < VCC < 1.71V; VOL = 0.2 VCC DS1374-18 Active Supply Current (Notes 11, 12) ICCA DS1374-3 DS1374-33 DS1374-18 Standby Current (Notes 11, 13) VBACKUP Leakage Current (VBACKUP = 3.7V) ICCS DS1374-3 DS1374-33 IBACKUPLKG 75 110 180 60 80 115 (Note 5) (Note 6) (Note 7) (Note 8) (Note 9) (Note 10) -1 -1 -200 CONDITIONS MIN TYP 250 2000 4000 +1 +1 +1 3.0 3.0 3.0 250 150 200 300 100 125 175 100 nA A A mA mA A A MAX UNITS
DS1374
DC ELECTRICAL CHARACTERISTICS
(VCC = 0V, VBACKUP = 3.7V, TA = -40C to +85C, unless otherwise noted.) (Note 1)
PARAMETER VBACKUP Current (OSC ON); SQW OFF VBACKUP Current (OSC ON); SQW ON (32kHz) VBACKUP Data-Retention Current (OSC OFF) SYMBOL IBKOSC1 IBKOSC2 IBACKUPDR (Note 14) (Notes 14, 15) CONDITIONS MAX TYP 400 600 25 MAX 700 1000 100 UNITS nA nA nA
_____________________________________________________________________
3
I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output DS1374
AC ELECTRICAL CHARACTERISTICS
(VCC = VCC MIN to VCC MAX, TA = -40C to +85C, unless otherwise noted.) (Note 1) (Figure 1)
PARAMETER SCL Clock Frequency (Note 16) Bus Free Time Between STOP and START Conditions Hold Time (Repeated) START Condition (Note 17) Low Period of SCL Clock High Period of SCL Clock Data Hold Time (Notes 18, 19) Data Setup Time (Note 20) Start Setup Time Rise Time of Both SDA and SCL Signals (Note 16) Fall Time of Both SDA and SCL Signals (Note 16) Setup Time for STOP Condition Capacitive Load for Each Bus Line I/O Capacitance (SDA, SCL) Pulse Width of Spikes That Must be Suppressed by the Input Filter Pushbutton Debounce Reset Active Time Oscillator Stop Flag (OSF) Delay SYMBOL fSCL tBUF tHD:STA tLOW tHIGH tHD:DAT tSU:DAT tSU:STA tR tF tSU:STO CB CI/O tSP PBDB tRST tOSF Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode (Note 16) (Note 21) Fast mode (Figure 2) (Figure 2) (Note 22) 30 250 250 100 CONDITIONS MIN 100 0 1.3 4.7 0.6 4.0 1.3 4.7 0.6 4.0 0 0 100 250 0.6 4.7 20 + 0.1CB 20 + 0.1CB 0.6 4.7 400 10 300 1000 300 300 0.9 0.9 TYP MAX 400 100 UNITS kHz s s s s s ns s ns ns s pF pF ns ms ms ms
4
_____________________________________________________________________
I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output
POWER-UP/POWER-DOWN CHARACTERISTICS
(TA = -40C to +85C) (Figure 3)
PARAMETER VCC Detect to Recognize Inputs (VCC Rising) VCC Fall Time; VPF(MAX) to VPF(MIN) VCC Rise Time; VPF(MIN) to VPF(MAX) SYMBOL tRPU tF tR (Note 23) 300 0 CONDITIONS MIN TYP 250 MAX UNITS ms s s
DS1374
WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when the device is in write protection. Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: Note 14: Note 15: Note 16: Note 17: Note 18: Note 19: Note 20: Limits at -40C are guaranteed by design and not production tested. All voltages are referenced to ground. VBACKUP should not exceed VCC MAX or 3.7V, whichever is greater. The use of the 250 trickle-charge resistor is not allowed at VCC > 3.63V and should not be enabled. Measured at VCC = typ, VBACKUP = 0V, register 09h = A5h. Measured at VCC = typ, VBACKUP = 0V, register 09h = A6h. Measured at VCC = typ, VBACKUP = 0V, register 09h = A7h. SCL only. SDA and SQW and INT. The RST pin has an internal 50k pullup resistor to VCC. Trickle charger disabled. ICCA--SCL clocking at max frequency = 400kHz. Specified with I2C bus inactive. Measured with a 32.768kHz crystal attached to the X1 and X2 pins. WDSTR = 1. BBSQW = 1 is required for operation when VCC is below the power-fail trip point (or absent). CB--total capacitance of one bus line in pF. After this period, the first clock pulse is generated. The maximum tHD:DAT only has to be met if the device does not stretch the low period (tLOW) of the SCL signal. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the VIHMIN of the SCL signal) to bridge the undefined region of the falling edge of SCL. A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT to 250ns must be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line tR max + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released. Guaranteed by design. Not production tested. The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of 0V VCC VCC MAX and 1.3V VBACKUP 3.7V. This delay applies only if the oscillator is enabled and running. If the EOSC bit is 1, the startup time of the oscillator is added to this delay.
Note 21: Note 22: Note 23:
_____________________________________________________________________
5
I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output DS1374
SDA
tBUF tLOW tR tF
tHD:STA
tSP
SCL tHD:STA STOP START tHD:DAT tHIGH tSU:DAT REPEATED START tSU:STA tSU:STO
Figure 1. Data Transfer on I2C Serial Bus
RST
PBDB
tRST
Figure 2. Pushbutton Reset Timing
VCC VPF(MAX) VPF(MIN) tF
VPF
VPF
tR tRPU tRST
RST
INPUTS
RECOGNIZED
DON'T CARE
RECOGNIZED
HIGH-Z OUTPUTS VALID VALID
Figure 3. Power-Up/Power-Down Timing
6
_____________________________________________________________________
I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output DS1374
Typical Operating Characteristics
(VCC = +3.3V, TA = +25C, unless otherwise noted.)
IBAT0SC1 vs. VBAT SQUARE-WAVE OFF
DS1374 toc01
IBAT0SC2 vs. VBAT SQUARE-WAVE ON
DS1374 toc02
IBATOSC1 vs. TEMPERATURE VBAT = 3.0V
VCC = 0V 450
DS1374 toc03
550 VCC = 0V 500 SUPPLY CURRENT (nA)
475
800 750 SUPPLY CURRENT (nA) 700 650 600 550 500 450 400
VCC = 0V
450
SUPPLY CURRENT (nA) 1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3
425
400
350
400
300 1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 VBAT (V)
350 VBAT (V)
375 -40 -20 0 20 40 60 80 TEMPERATURE (C)
ICCA vs. VCC (SQUARE-WAVE ON)
DS1374 toc04
OSCILLATOR FREQUENCY vs. VBACKUP
32768.7 32768.6 FREQUENCY (Hz) 32768.5 32768.4 32768.3 32768.2 32768.1 32768.0 VCC = 0V
DS1374 toc05
275 250 SUPPLY CURRENT (A) 225 200 175 150 125 100 75 50 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 VCC (V)
32768.8
1.3
1.8
2.3
2.8
3.3
3.8
4.3
4.8
5.3
VBACKUP (V)
VCC FALLING vs. RST DELAY
VCC = 3.0V TO 0V 100 RESET DELAY (s)
DS1374 toc06
1000
10
1
0.1 0.01 0.10 1 10 100 VCC FALLING (V/ms)
_____________________________________________________________________
7
I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output DS1374
Pin Description
PIN SOP SO NAME FUNCTION Connections for a Standard 32.768kHz Quartz Crystal. The internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (CL) of 6pF. Pin X1 is the input to the oscillator and can optionally be connected to an external 32.768kHz oscillator. The output of the internal oscillator, pin X2, is floated if an external oscillator is connected to pin X1. Connection for a Secondary Power Supply. Supply voltage must be held between 1.3V and 3.7V (-18 and -3) or 1.3V and 5.5V (-33) for proper operation. This pin can be connected to a primary cell such as a lithium button cell. Additionally, this pin can be connected to a rechargeable cell or a super cap when used with the trickle-charge feature. UL recognized to ensure against reverse charging when used with a lithium battery. Active-Low, Open-Drain Output with a Debounced Pushbutton Input. This pin can be activated by a pushbutton reset request, a watchdog alarm condition, or a power-fail event. It has an internal 50k pullup resistor. Ground Serial Data Input/Output. SDA is the input/output for the 2-wire serial interface. The SDA pin is open drain and requires an external pullup resistor. Serial Clock Input. SCL is the clock input for the 2-wire serial interface and is used to synchronize data movement on the serial interface. Interupt. This pin is used to output the alarm interrupt or the watchdog reset signal. It is active-low open drain and requires an external pullup resistor. Square-Wave Output. This pin is used to output the programmable square-wave signal. It is open drain and requires an external pullup resistor. DC Power for Primary Power Supply No Connection. Must be connected to ground.
1, 2
--
X1, X2
3
13
VBACKUP
4 5 6 7 8 9 10 --
14 15 16 1 2 3 4 5-12
RST GND SDA SCL INT SQW VCC N.C.
X1 X2 CLOCK DIVIDER
1Hz 4.096kHz 8.192kHz 32.768kHz 32-BIT COUNTER ALARM/ WATCHDOG STAT/CTRL/ TRICKLE
MUX
SQW 1Hz/0.96kHz INT CONTROL 24-BIT COUNTER INT
VCC VBACKUP GND
POWER CONTROL AND TRICKLE CHARGE 2-WIRE INTERFACE
SDA SCL
RST CONTROL
RST
DS1374
Figure 4. Functional Diagram
8
_____________________________________________________________________
I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output DS1374
Table 1. Crystal Specifications*
PARAMETER Nominal Frequency Series Resistance Load Capacitance SYMBOL fO ESR CL 6 MIN TYP 32.768 45 MAX UNITS kHz
CRYSTAL X1 LOCAL GROUND PLANE (LAYER 2)
k pF
X2
*The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for additional specifications.
GND
NOTE: AVOID ROUTING SIGNALS IN THE CROSSHATCHED AREA (UPPER LEFT-HAND QUADRANT) OF THE PACKAGE UNLESS THERE IS A GROUND PLANE BETWEEN THE SIGNAL LINE AND THE PACKAGE.
Figure 6. Layout Example
COUNTDOWN CHAIN
Clock Accuracy
Clock accuracy is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional error is added by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the oscillator circuit can result in the clock running fast. Figure 6 shows a typical PC board layout for isolating the crystal and oscillator from noise. Refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks for detailed information.
DS1374
CL1 CL2 RTC REGISTERS
X1
X2
CRYSTAL
Figure 5. Oscillator Circuit Showing Internal Bias Network
Detailed Description
The DS1374 is a real-time clock with an I2C serial interface. It provides elapsed seconds from a user-defined starting point in a 32-bit counter (Figure 4). A 24-bit counter can be configured as either a watchdog counter or an alarm counter. An on-chip oscillator circuit uses a customer-supplied 32.768kHz crystal to keep time. A power-control circuit switches operation from VCC to VBACKUP and back when power on VCC is cycled. If a rechargeable backup supply is used, a trickle charger can be enabled to charge the backup supply while VCC is on.
DS1374C Only
The DS1374C integrates a standard 32,768Hz crystal into the package. Typical accuracy at nominal VCC and 25C is approximately 10ppm. See Application Note 58 for information about crystal accuracy vs. temperature.
Address Map
Table 2 shows the address map for the DS1374 registers. During a multibyte access, the address pointer wraps around to location 00h when it reaches the end of the register space (08h). On an I2C START, STOP, or address pointer incrementing to location 00h, the current time is transferred to a second set of registers. These secondary registers read the time information, while the clock continues to run. This eliminates the need to reread the registers in case of an update of the main registers during a read.
Oscillator Circuit
The DS1374 uses an external 32.768kHz crystal. The oscillator circuit does not require any external resistors or capacitors to operate. Table 1 specifies several crystal parameters for the external crystal. Figure 5 shows a functional schematic of the oscillator circuit. The startup time is usually less than 1 second when using a crystal with the specified characteristics.
Time-of-Day Counter
The time-of-day counter is a 32-bit up counter. The contents can be read or written by accessing the
9
_____________________________________________________________________
I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output DS1374
Table 2. Address Map
ADDRESS 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H EOSC OSF TCS3 WACE 0 TCS2 WD/ALM 0 TCS1 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FUNCTION Time-of-Day Counter Time-of-Day Counter Time-of-Day Counter Time-of-Day Counter Watchdog/Alarm Counter Watchdog/Alarm Counter Watchdog/Alarm Counter RS2 0 DS0 RS1 0 ROUT1 AIE AF ROUT0 Control Status Trickle Charger TOD Counter Byte 0 TOD Counter Byte 1 TOD Counter Byte 2 TOD Counter Byte 3 WD/ALM Counter Byte 0 WD/ALM Counter Byte 1 WD/ALM Counter Byte 2 BBSQW 0 TCS0 WDSTR 0 DS1
Note: Unless otherwise specified, the state of the registers is not defined when power is first applied.
address range 00h-03h. When the counter is read, the current time of day is latched into a register, which is output on the serial data line while the counter continues to increment.
Watchdog/Alarm Counter
The contents of the watchdog/alarm counter, which is a separate 24-bit down counter, are accessed in the address range 04h-06h. When this counter is written, the counter and a seed register are loaded with the desired value. When the counter is to be reloaded, it uses the value in the seed register. When the counter is read, the current counter value is latched into a register, which is output on the serial data line while the counter continues to decrement. If the counter is not needed, it can be disabled and used as a 24-bit cache of NV RAM by setting the WACE bit in the control register to logic 0. If all 24 bits of the watchdog/alarm counter are written to zero when WACE = 1, the counter is disabled and the AF bit is not set. When the WD/ALM bit in the control register is set to a logic 0, the WD/ALM counter decrements every second until it reaches zero. At this point, the AF bit in the status register is set and the counter is reloaded and restarted. If AF is set when the watchdog function is enabled, the output selected by WDSTR immediately becomes active. When the WD/ALM bit is set to logic 1, the WD/ALM counter decrements every 1/4096 of a second (approximately every 244s) until it reaches zero, sets the AF bit in the status register, and stops. If WDSTR = 0, the RST pin pulses low for 250ms, and accesses to the DS1374 are inhibited. At the end of the 250ms pulse, the AF bit is cleared to zero, the RST pin becomes high impedance, and read/write access to the DS1374 is enabled. If AIE =
10
1 and WDSTR = 1, the INT pin pulses low for 250ms. The pulse cannot be truncated by writing either AF or AIE to zero during the low time of the INT pin. If the WD/ALM counter is written during the 250ms pulse, the counter starts decrementing upon the pulse completion. At the completion, the AF bit clears to zero and the INT pin becomes high impedance. The WD/ALM counter can be reloaded and restarted before the counter reaches zero by reading or writing any of the WD/ALM counter registers.
Power-Up/Power-Down Reset and Pushbutton Reset Functions
A precision temperature-compensated reference and comparator circuit monitors the status of VCC. When an out-of-tolerance condition occurs, an internal power-fail signal is generated that forces the RST pin low and blocks read/write access to the DS1374. When VCC returns to an in-tolerance condition, the RST pin is held low for 250ms to allow the power supply to stabilize. If the EOSC bit is set to a logic 1 (to disable the oscillator in battery-backup mode), the reset signal is kept active for 250ms plus the startup time of the oscillator. The DS1374 provides for a pushbutton switch to be connected to the RST output pin. When the DS1374 is not in a reset cycle, it continuously monitors the RST signal for a low-going edge. If an edge is detected, the DS1374 debounces the switch by pulling the RST pin low and inhibits read/write access. After the internal 250ms timer has expired, the device continues to monitor the RST line. If the line is still low, the DS1374 continues to monitor the line, looking for a rising edge. Upon detecting release, the DS1374 forces the RST pin low and holds it low for an additional 250ms.
____________________________________________________________________
I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output DS1374
Bit 7 EOSC Bit 6 WACE Bit 5 WD/ALM Bit 4 BBSQW Bit 3 WDSTR Bit 2 RS2 Bit 1 RS1 Bit 0 AIE
Special Purpose Registers
The DS1374 has two additional registers (07h-08h) that control the WD/ALM counter and the square-wave, interrupt, and reset outputs.
Control Register (07h)
Bit 7/Enable Oscillator (EOSC). When set to logic 0, the oscillator is started. When set to logic 1, the oscillator is stopped. When this bit is set to logic 1, the oscillator is stopped and the DS1374 is placed into a low-power standby mode (IDDR). This bit is clear (logic 0) when power is first applied. When the DS1374 is powered by VCC, the oscillator is always on regardless of the state of the EOSC bit. A Bit 6/WD/ALM Counter Enable (WACE). When set to logic 1, the WD/ALM counter is enabled. When set to logic 0, the WD/ALM counter is disabled, and the 24 bits can be used as NV RAM. This bit is clear (logic 0) when power is first applied. A Bit 5/WD/ALM Counter Select (WD/ALM). When set to logic 0, the counter decrements every second until it reaches zero and is then reloaded and restarted. When set to logic 1, the WD/ALM counter decrements every 1/4096 of a second (approximately every 244s) until it reaches zero, sets the AF bit in the status register, and stops. If any of the WD/ALM counter registers are accessed before the counter reaches zero, the counter is reloaded and restarted. This bit is clear (logic 0) when power is first applied.
Bit 4/Battery-Backed Square-Wave Enable (BBSQW). This bit, when set to logic 1, enables the square-wave output when VCC is absent and when the DS1374 is being powered by the VBACKUP pin. When BBSQW is logic 0, the SQW pin goes high impedance when VCC falls below the power-fail trip point. This bit is disabled (logic 0) when power is first applied. Bit 3/Watchdog Reset Steering Bit (WDSTR). This bit selects which output pin the watchdog-reset signal occurs on. When the WDSTR bit is set to logic 0, a 250ms pulse occurs on the RST pin if WD/ALM = 1 and the WD/ALM counter reaches zero. The 250ms reset pulse occurs on the INT pin when the WDSTR bit is set to logic 1. This bit is logic 0 when power is first applied. Bits 2, 1/Rate Select (RS2 and RS1). These bits control the frequency of the square-wave output when the square wave has been enabled. Table 3 shows the square-wave frequencies that can be selected with the RS bits. These bits are both set (logic 1) when power is first applied. Bit 0/Alarm Interrupt Enable (AIE). When set to logic 1, this bit permits the alarm flag (AF) bit in the status register to assert INT (when INTCN = 1). When set to logic 0 or INTCN is set to logic 0, the AF bit does not initiate the INT signal. If the WD/ALM bit is set to logic 1 and the AF flag is set, writing AIE to zero does not truncate the 250ms pulse on the INT pin. The AIE bit is at logic 0 when power is first applied. The INT output is available while the device is powered by either supply.
Table 4. Trickle Charge Register
TCS3 X X X 1 1 1 1 1 1 0 TCS2 X X X 0 0 0 0 0 0 0 TCS1 X X X 1 1 1 1 1 1 0 TCS0 X X X 0 0 0 0 0 0 0 DS1 0 1 X 0 1 0 1 0 1 0 DS0 0 1 X 1 0 1 0 1 0 0 ROUT1 X X 0 0 0 1 1 1 1 0 ROUT0 X X 0 1 1 0 0 1 1 0 Disabled Disabled Disabled No diode, 250 resistor One diode, 250 resistor No diode, 2k resistor One diode, 2k resistor No diode, 4k resistor One diode, 4k resistor Power-on reset value FUNCTION
____________________________________________________________________
11
I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output DS1374
Bit 7 OSF Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 AF
Table 3. Square-Wave Output Frequency
RS2 0 0 1 1 RS1 0 1 0 1 SQUARE-WAVE OUTPUT FREQUENCY 1Hz 4.096kHz 8.192kHz 32.768kHz
cleared when written to logic 0. This bit can only be written to logic 0. Attempting to write logic 1 leaves the value unchanged. If WD/ALM is set to 1 and the AIE bit = 1, the INT pin pulses low for 250ms when the WD/ALM counter reaches zero and sets AF = 1. At the pulse completion, the DS1374 clears the AF bit to zero. If the 250ms pulse is active, writing AF to zero does not truncate the pulse.
Status Register (08h)
Bit 7/Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator either is stopped or was stopped for some period of time and can be used to judge the validity of the timekeeping data. This bit is set to logic 1 any time the oscillator stops. The following are examples of conditions that can cause the OSF bit to be set: 1) The first time power is applied. 2) The voltage present on VCC is insufficient to support oscillation. 3) The EOSC bit is turned off. 4) External influences on the crystal (i.e., noise, leakage, etc.). This bit remains at logic 1 until written to logic 0. Bit 0/Alarm Flag (AF). A logic 1 in the alarm flag bit indicates that the WD/ALM counter reached zero. If WD/ALM is set to zero and the AIE bit = 1, the INT pin goes low and stays low until AF is cleared. AF is
BIT 7 TCS3 BIT 6 TCS2 BIT 5 TCS1 BIT 4 TCS0 BIT 3 DS1 BIT 2 DS0 BIT 1 BIT 0 ROUT1 ROUT0
Trickle-Charge Register (10h)
The simplified schematic in Figure 7 shows the basic components of the trickle charger. The trickle-charge select (TCS) bits (bits 4-7) control the selection of the trickle charger. To prevent accidental enabling, only a pattern of 1010 enables the trickle charger. All other patterns disable the trickle charger. The trickle charger is disabled when power is first applied. The diode select (DS) bits (bits 2, 3) select whether or not a diode is connected between VCC and VBACKUP. If DS is 01, no diode is selected; if DS is 10, a diode is selected. The ROUT bits (bits 0, 1) select the value of the resistor connected between VCC and VBACKUP. Table 4 shows the resistor selected by the resistor select (ROUT) bits and the diode selected by the diode select (DS) bits. Warning: The ROUT value of 250 must not be selected whenever VCC is greater than 3.63V. The user determines diode and resistor selection according to the maximum current desired for battery or super cap charging. The maximum charging current can be calculated as illustrated in the following example.
1 OF 16 SELECT NOTE: ONLY 1010b ENABLES CHARGER
TCS0-3 = TRICKLE CHARGER SELECT DS0-1 = DIODE SELECT TOUT0-1 = RESISTOR SELECT 1 OF 2 SELECT 1 OF 3 SELECT
R1 250 R2 2k R3 4k
VCC
VBACKUP
Figure 7. Programmable Trickle Charger 12 ____________________________________________________________________
I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output DS1374
SDA
MSB SLAVE ADDRESS R/W DIRECTION BIT ACKNOWLEDGEMENT SIGNAL FROM RECEIVER SCL 1 START CONDITION 2 6 7 8 9 ACK REPEATED IF MORE BYTES ARE TRANSFERED 1 2 3-7 8 9 ACK STOP CONDITION OR REPEATED START CONDITION ACKNOWLEDGEMENT SIGNAL FROM RECEIVER
Figure 8. I2C Data Transfer Overview
Assume that a system power supply of 3.3V is applied to VCC and a super cap is connected to VBACKUP. Also assume the trickle charger has been enabled with a diode and resistor R2 between VCC and VBACKUP. The maximum current IMAX would therefore be calculated as follows: IMAX = (3.3V - diode drop) / R2 (3.3V - 0.7V) / 2k 1.3mA As the super cap changes, the voltage drop between VCC and VBACKUP decreases and therefore the charge current decreases.
data line while the clock line is high can be interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain high. Start data transfer: A change in the state of the data line from high to low, while the clock line is high, defines a START condition. Stop data transfer: A change in the state of the data line from low to high, while the clock line is high, defines a STOP condition. Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between the START and the STOP conditions is not limited, and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. A standard mode (100kHz clock rate) and a fast mode (400kHz clock rate) are defined within the I2C bus specifications. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit.
13
I2C Serial Data Bus
The DS1374 supports the I2C bus protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data is a receiver. The device that controls the message is called a master. The devices that are controlled by the master are slaves. A master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions must control the bus. The DS1374 operates as a slave on the I2C bus. Connections to the bus are made through the open-drain I/O lines SDA and SCL. A standard mode (100kHz max clock rate) and a fast mode (400kHz max clock rate) are defined within the bus specifications. The DS1374 works in both modes. The following bus protocol has been defined (Figure 8): * Data transfer can be initiated only when the bus is not busy. * During data transfer, the data line must remain stable whenever the clock line is high. Changes in the
____________________________________________________________________
I2C, 32-Bit Binary Counter Watchdog RTC with Tickle Charger and Reset Input/Output DS1374
R/W
SLAVE ADDRESS S 1101000 REGISTER ADDRESS (n)
R/W
DATA (n) XXXXXXXX A
DATA (n + 1)
DATA (n + x) P
SLAVE ADDRESS S 1101000
DATA (n)
DATA (n + 1) XXXXXXXX A
DATA (n + 2)
DATA (n + x) /A
0 A XXXXXXXX A
XXXXXXXX A XXXXXXXX DATA TRANSFERRED (X+1 Bytes + Acknowledge)
1 A XXXXXXXX A
XXXXXXXX A XXXXXXXX
S - START A - ACKNOWLEDGE P - STOP R/W - READ/WRITE OR DIRECTION BIT
S - START A - ACKNOWLEDGE P - STOP /A - NOT ACKNOWLEDGE R/W - READ/WRITE OR DIRECTION BIT
DATA TRANSFERRED (X+1 Bytes + Acknowledge)
Figure 9. I2C Write Protocol
Figure 10. I2C Read Protocol
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge-related clock pulse. Setup and hold times must be considered. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the STOP condition. Figures 9 and 10 detail how data transfer is accomplished on the 2-wire bus. Depending on the state of the R/W bit, two types of data transfer are possible: Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the slave address). The slave then returns an acknowledge bit. Next follows a number of data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a "not acknowledge" is returned. The master device generates the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus is not released. The DS1374 can operate in the following two modes: Slave Receiver Mode (Write Mode): Serial data and clock data are received through SDA and SCL. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware
after reception of the slave address and direction bit. The slave address byte is the first byte received after the master generates a START condition. The slave address byte contains the 7-bit DS1374 address, which is 1101000, followed by the direction bit (R/W), which is zero for a write. After receiving and decoding the slave address byte, the DS1374 outputs an acknowledge on SDA. After the DS1374 acknowledges the slave address + write bit, the master transmits a register address to the DS1374. This sets the register pointer on the DS1374, with the DS1374 acknowledging the transfer. The master can then transmit zero or more bytes of data, with the DS1374 acknowledging each byte received. The register pointer increments after each data byte is transferred. The master generates a STOP condition to terminate the data write. Slave Transmitter Mode (Read Mode): The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the DS1374, while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit. The slave address byte is the first byte received after the START condition is generated by the master. The slave address byte contains the 7-bit DS1374 address, which is 1101000, followed by the direction bit (R/W), which is 1 for a read. After receiving and decoding the slave address byte, the DS1374 outputs an acknowledge on SDA. The DS1374 then begins to transmit data starting with the register address pointed to by the register pointer. If the register pointer is not written to before the initiation of a read mode, the first address that is read is the last one stored in the register pointer. The DS1374 must receive a not acknowledge to end a read.
14
____________________________________________________________________
I2C, 32-Bit Binary Counter Watchdog RTC with Tickle Charger and Reset Input/Output
Handling, PC Board Layout, and Assembly
The DS1374C package contains a quartz tuning-fork crystal. Pick-and-place equipment can be used, but precautions should be taken to ensure that excessive shocks are avoided. Ultrasonic cleaning should be avoided to prevent damage to the crystal. Avoid running signal traces under the package, unless a ground plane is placed between the package and the signal line. All no connect (N.C.) pins must be connected to ground. The SO package can be reflowed as long as the peak temperature does not exceed 240C. Peak reflow temperature ( 230C) duration should not exceed 10 seconds, and the total time above 200C should not exceed 40 seconds (30 seconds nominal). Exposure to reflow is limited to 2 times maximum. Moisture-sensitive packages are shipped from the factory dry-packed. Handling instructions listed on the package label must be followed to prevent damage during reflow. Refer to the IPC/JEDEC J-STD-020B standard for moisture-sensitive device (MSD) classifications.
Chip Information
TRANSISTOR COUNT: 11,036 PROCESS: CMOS SUBSTRATE CONNECTED TO GROUND
DS1374
Thermal Information
Theta-JA: 221C/W (SOP) Theta-JC: 39C/W (SOP) Theta-JA: 73C/W (16 SO) Theta-JC: 23C/W (16 SO)
Package Information
(For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.)
Pin Configurations
TOP VIEW
SCL X1 1 X2 VBACKUP RST GND 2 3 4 5 10 VCC INT SQW VCC N.C. N.C. 9 8 7 6 SQW INT SCL SDA 3 4 5 6 7 8 14 RST VBACKUP N.C. N.C. N.C. N.C. 13 12 11 10 9 1 2 16 15 SDA GND
DS1374
DS1374C
SOP
N.C. N.C.
SO (0.300")
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
is a registered trademark of Dallas Semiconductor Corporation.

▲Up To Search▲

Price & Availability of DS1374C-33

	To Download DS1374C-33 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .